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low power 165 mhz hdmi receiver data sheet adv7611 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may r esult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 - 2012 analog devices, inc. all rights reserved. features high - definition multimedia interface (hdmi ? ) 1.4a features supported all m andatory and additional 3d v ideo format s suppor ted extended colorimetry, including sycc601 , adobe rgb, adobe ycc 601 , xvycc extended gamut color cec 1.4 - compatible hdmi rece iver 165 mhz maxi mum tmds clock frequency 24- bit output pixel bus high - bandwidth d igital content protection (hdcp) 1.4 support with internal hdcp keys hdcp r epeater s upport up to 127 ksvs supported integrated cec c ontroller programmable hdmi e quali z er 5 v d etect and h ot p lug a ssert for hdmi port audio support s pdif (iec 60958 - compatible) digital audio hdmi audio extraction support advance d audio mute feature general interrupt controller with two interrupt outputs standard i dentification (stdi) circuit high ly flexible 24- bit pixel output interface internal edid ram any - to - any 3 3 color space conversion (csc) matrix 2 - layer pcb design supported 64- lead lqfp_ep, 1 0 mm 1 0 mm package qualified for automotive applications applications projectors automotive v ideo conferencing hdtv s avr, htib soundbar s video switch es functional block dia gram hs/vs 4 i 2 s s/pdif hdcp keys tmds ddc hdmi1 deep color hdmi rx adv7611 component processor 36 output mux field/de llc data mclk sclk lrclk lrclk ap mclk sclk output mux 24-bit ycbcr/rgb hs vs/field de llc 09305-001 figure 1 .
adv7611 data sheet rev. d | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 detailed functional block diagram .......................................... 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 data and i 2 c timing characteristics ......................................... 5 absolute maximum ratings ............................................................ 7 package thermal performance ................................................... 7 esd caution .................................................................................. 7 pin configuration and fu nction descriptions ............................. 8 power supply sequencing .............................................................. 10 power - up sequence ................................................................... 10 power - down sequence .............................................................. 10 functional overview ...................................................................... 11 hdmi receiver ........................................................................... 11 component processor ............................................................... 11 other features ............................................................................ 11 pixel input/output formatting .................................................... 12 pixel data output modes features .......................................... 12 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 automotive products ................................................................. 14 revision history 6/12 rev. c to r e v. d change to pin 1 description, table 4 ............................................. 8 5 /12 rev. b to rev. c changes to features section ............................................................ 1 changes to general description section ...................................... 3 added endnote 3 (table 1) ............................................................. 4 deleted tdm serial timing parameter (table 2) ........................ 5 deleted figure 6 ................................................................................ 7 change d pin 48 description ( table 4 ) .......................................... 9 changes to hdmi receive r and other features sections ........ 11 added endnote 1 in pixel input/output formatting sect ion and end note 1 to table 5 ....................................................................... 12 deleted time - division multiplexed (tdm) mode section and figure 9 ..................................................................................... 13 changes to p14 (table 6) ............................................................... 13 changes to ordering guide .......................................................... 14 added hdmi note ......................................................................... 16 6 /11 rev. a to rev. b changes to figure 7 .......................................................................... 1 5 /11 rev. 0 to rev. a changes to features sec tion ............................................................ 1 changes to ordering guide .......................................................... 16 added automotive products section .......................................... 16 11/10 revision 0: initial version
data sheet adv7611 rev. d | page 3 of 16 general description the adv7611 is offered in automotive, professional (no hdcp) , and industrial versions. the operating temperature range is ?40 o c to +85 o c. the ug - 180 contains critical information that must be used in conjunction with the adv7611. the adv7611 is a high quality, single input hdmi ? - capable receiver. it incorporates an hdmi - capable receiver that supports all mandatory 3d tv defined in hdmi 1.4a. the adv7611 supports formats up to uxga 60 hz at 8 bit. it integrates a cec controller that supports the c apability discovery and c ontrol (cdc) feature. the adv7611 has an audio output port for the audio data extracted from the hdmi stream. the hdmi receiver has an advanced mute controller that prevents audible extraneous noise in the audio output. the following audio formats are accessible: ? a stream from the i 2 s serializer (two audio channels) ? a stream from the s/pdif serializer (two uncompres sed channels or n compressed channels, for example, ac3) ? dst stream the hdmi port has dedicated 5 v d etect and hot plug ? a ssert pins. the hdmi receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cab les . the adv7611 contains one main component pro cessor (cp), that processes the video signals from the hdmi receiver. it provides features such as contrast, brightness and saturation adjustments, stdi detection block, free run, and synchronization alignmen t controls. fabricated in an advanced cmos process, the adv7611 is provided in a 10 mm 10 mm, 64 - lead surface - mount lqfp _ep, rohs - compliant pac kage and is specified over the ? 40 c to + 85 c tempera ture range . detailed functional block diagram control interface i 2 c control and data pll edid repeater controller hdcp engine packet/ infoframe memory 12 12 12 backend colorspace conversion o u t p u t f o r m a t t e r component processor 5v detect and hpd controller audio processor data preprocesor and color space conversion hdmi processor packet processor a b c mute interrupt controller (int1,int2) p0 to p7 *int2 can be only output on one of the pins: sclk/int2, mclk/int2, or hpa_a/int2. xtalp xtaln scl sda cec rxa_5v hpa_a/int2* ddca_sda ddca_scl rxa_c rxa_0 rxa_1 rxa_2 p8 to p15 p16 to p23 llc hs vs/field/alsb de int1 int2* ap lrclk sclk/int2* mclk/int2* audio output formatter hdcp eeprom sampler equalizer dpll cec controller adv7611 09305-002 figure 2 . detailed functional block diagram
adv7611 data sheet rev. d | page 4 of 16 specifications at dvdd = 1.71 v to 1.89 v, dvddio = 3.14 v to 3.46 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.14 v to 3 .46 v, cvdd = 1.71 v to 1.89 v , t min to t max = ? 40c to +85c, unless otherwise noted . electrical character istics table 1. parameter symbol test conditions /comments min typ max unit digital inputs 1 input high voltage v ih xt aln and xtalp 1.2 v v ih other digital inputs 2 v input low voltage v il xtaln and xtalp 0.4 v v il other digital inputs 0.8 v input current i in reset pin 45 60 a other digital inputs 10 a input capacitance c in 10 pf digital inputs (5 v tolerant) 1 , 2 input high voltage v ih 2.6 v input low voltage v il 0.8 v input current i in ? 82 +82 a digital outputs 1 output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak vs/field/alsb pin 35 60 a hpa_a/int2 pin 82 a other 10 a output c apacitance c out 20 pf power requirements 3 , 4 digital core power supply d vdd 1.71 1.8 1.89 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pvdd 1.71 1.8 1.89 v terminator power supply tvdd 3.14 3.3 3.46 v comparator pow er supply cvdd 1.71 1.8 1.89 v digital core supply current i dvdd uxga 60 hz at 8 bit 95.7 188.1 ma digital i/o supply current i dvddio uxga 60 hz at 8 bit 12.9 178.5 ma pll supply current i pvdd uxga 60 hz at 8 bit 30.7 36.9 ma terminator supply curr ent i tvdd uxga 60 hz at 8 bit 50.9 57.6 ma comparator supply current i cvdd uxga 60 hz at 8 bit 95.8 114.4 ma p ower - down c urrents 3 , 5 digital core supply current i dvdd _pd power - down mode 1 0.2 0.5 ma digital i/o s upply current i dvddio _pd power - down mode 1 1.3 1.7 ma pll supply current i pvdd _pd power - down mode 1 1.5 1.8 ma terminator supply current i tvdd _pd power - down mode 1 0.1 0.3 ma comparator supply current i cvdd _pd power - down mode 1 1.3 1.7 ma power - up time t pwrup 25 ms 1 data guaranteed by characterization . 2 the following pins are 5 v tolerant: ddca_scl, ddc_sda , and rxa_5v. 3 data recor ded during lab characterization . 4 maximum current consumption values are recorded with maximum rated voltage supply levels, moirex video pattern, a nd at maximum rated temperature. 5 power - down mode 0 (io m ap , r eg ister 0x0c = 0x62), ring o sci llator powered down (hdmi m ap, r eg ister 0x48 = 0x01) , and ddc p ads off (hdmi m ap, r eg ister 0x73 = 0x01) .
data sheet adv7611 rev. d | page 5 of 16 data and i 2 c timing characteristics table 2. parameter symbol test conditions/comments min typ max unit clock and crystal crystal frequency, xtalp 28.63636 mhz crystal frequency stabi lity 50 ppm llc frequency range 1 13.5 165 mhz i 2 c ports scl frequency 400 khz scl minimum pulse width high 2 t 1 600 ns scl minimum pulse width low 2 t 2 1.3 s start condition hold time 2 t 3 600 ns start condition setup time 2 t 4 600 ns sda setup time 2 t 5 100 ns scl and sda rise time 2 t 6 300 ns scl and sda fall time 2 t 7 300 ns stop condition setup time 2 t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc mark-space ratio 2 t 9 :t 10 45:55 55:45 % duty cycle data and control outputs 3 data output transition time 2 , 4 t 11 end of valid data to negati ve clock edge 1.0 2.2 ns t 12 negative clock edge to start of valid data 0.0 0.3 ns i 2 s port, master mode sclk mark-space ratio 2 t 15 :t 16 45:55 55:45 % duty cycle lrclk data transition time 2 t 17 end of valid data to negative sclk edge 10 ns lrclk data transition time 2 t 18 negative sclk edge to start of valid data 10 ns i 2 s data transition time 2 , 5 t 19 end of valid data to negative sclk edge 5 ns i 2 s data transition time 2 , 5 t 20 negative sclk edge to start of valid data 5 ns 1 maximum llc frequency is limited by the clock frequency of uxga 60 hz at 8 bit. 2 data guaranteed by characterization. 3 with the dll block on output clock bypassed. 4 dll bypassed on clock path. 5 i 2 s is accessible via the ap pin.
adv7611 data sheet rev. d | page 6 of 16 ti ming diagrams s d a s c l t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 09305-003 figure 3 . i 2 c timing t 9 llc t 11 t 12 t 10 p0 to p23, hs, vs/field/alsb, de 09305-004 figure 4 . pixel port and co ntrol sdr output timing sclk lrclk i 2 s left-justified mode i 2 s right-justified mode i 2 s i 2 s mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. i 2 s is a signal accessible via the ap pin. 09305-005 figure 5 . i 2 s timing
data sheet adv7611 rev. d | page 7 of 16 abs olute maximum rating s table 3. parameter rating dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.3 v digital outputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v xtalp, xtaln gnd ? 0.3 v to pvdd + 0.3 v scl/sda data pins to dvddio dvddio ? 0.3 v to dvddio + 3.6 v maximum junction temperature ( t j max ) 125 c storage temperature range ? 60 c to + 150 c infrared reflow soldering (20 sec) 260 c 1 the following inputs are 3.3 v inputs but are 5 v tolerant: ddca_scl and ddca_sda . stresses above those listed under absolute maximum ratings may cause p ermanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. package thermal perf ormance to reduce power consumption when using the adv7611 , the user is advised to turn off the unused sections of the part. due to the printed circuit board ( pcb ) metal varia tion, and , therefore , variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the v ariance associated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction tempera - ture using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): ( ) total jt s j w t t + = where: t s is the package surface temperature (c). jt = 0.4c/w for the 64 - lead lqfp_ep. w total = ((pvdd i pvdd ) + (0.05 tvdd i tvdd ) + (cvdd i cvdd ) + ( d vdd i dv dd ) + (dvddio i dvddio )) where 0.05 is 5% of the tvdd power that is dissipated on the part itself. esd caution
adv7611 data sheet rev. d | page 8 of 16 pin configuration an d function descripti ons ap vs/field/alsb hs de dvddio p0 p1 p2 dvdd p3 p4 p5 p6 p7 dvddio p8 rxa_5v ddca_sda ddca_scl cec dvdd xtaln xtalp pvdd reset int1 sda scl dvdd mclk/int2 lrclk sclk/int2 p21 p20 p19 p18 p17 p16 dvddio dvdd llc p15 p14 p13 p12 p11 p10 p9 hpa_a/int2 cvdd rxa_c? rxa_c+ tvdd rxa_0? rxa_0+ tvdd rxa_1? rxa_1+ tvdd rxa_2? rxa_2+ cvdd p23 p22 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 1 1 47 46 45 42 43 44 48 41 40 39 37 36 35 34 33 38 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 adv76 1 1 t op view (not to scale) pin 1 indicator notes 1. connect exposed p ad (pin0) t o ground (bot t om). 09305-008 figure 6 . pin configuration table 4. pin function descriptions pin no. mnemonic type description 0 gnd ground ground. 1 hpa_a/int2 miscellaneous digital a dual function pin that can be configured to output a hot plug a ssert signal (for hdmi p ort a) or an interrupt 2 signal. this pin is 5 v tolerant. 2 cvdd power hdmi a nalog block supply voltage (1.8 v). 3 rxa_c ? hdmi input digital input clock complement of port a in the hdmi interface. 4 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. 5 tvdd power terminator supply voltage (3.3 v). 6 rxa_ 0? hdmi input digital input channel 0 complement of port a in the hdmi interface. 7 rxa_0+ hdmi input digital input channel 0 true of port a in the hdmi interface. 8 tvdd power terminator supply voltage (3.3 v). 9 rxa_1 ? hdmi input digital input channel 1 complement of port a in the hdmi interface. 10 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi interface. 11 tvdd power terminator supply voltage (3.3 v). 12 rxa_2 ? hdmi input digital input channel 2 complement of port a in the h dmi interface. 13 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface. 14 cvdd power hdmi analog block supply voltage (1.8 v). 15 p23 digital video output video pixel output port. 16 p22 digital video output video pixel outpu t port. 17 p21 digital video output video pixel output port. 18 p20 digital video output video pixel output port. 19 p19 digital video output video pixel output port. 20 p18 digital video output video pixel output port. 21 p17 digital video output vid eo pixel output port. 22 p16 digital video output video pixel output port. 23 dvddio power digital i/o supply voltage (3.3 v). 24 dvdd power digital core supply voltage (1.8 v).
data sheet adv7611 rev. d | page 9 of 16 pin no. mnemonic type description 25 llc digital video output line - locked output clock for the pixel data (r ange is 13.5 mhz to 162.5 mhz). 26 p15 digital video output video pixel output port. 27 p14 digital video output video pixel output port. 28 p13 digital video output video pixel output port. 29 p12 digital video output video pixel output port. 30 p11 digital video output video pixel output port. 31 p10 digital video output video pixel output port. 32 p9 digital video output video pixel output port. 33 p8 digital video output video pixel output port. 34 dvddio power digital i/o supply voltage (3.3 v ). 35 p7 digital video output video pixel output port. 36 p6 digital video output video pixel output port. 37 p5 digital video output video pixel output port. 38 p4 digital video output video pixel output port. 39 p3 digital video output video pixel o utput port. 40 dvdd power digital core supply voltage (1.8 v). 41 p2 digital video output video pixel output port. 42 p1 digital video output video pixel output port. 43 p0 digital video output video pixel output port. 44 dvddio power digital i/o supp ly voltage (3.3 v). 45 de miscellaneous digital de (data enable) is a signal that indicates active pixel data. 46 hs digital video output hs is a horizontal synchronization output signal. 47 vs/field/als b digital input/output vs is a vertical synchroni zation output signal. field is a field synchronization output signal in all interlaced video modes. vs or field can be configured for this pin. the alsb allows selection of the i 2 c address. 48 ap miscellaneous digital audio output pin. pin can be configur ed to output s / pdif digital audio output (s / pdif) or i 2 s. 49 sclk/int2 miscellaneous digital a dual function pin th at can be configured to output an a udio s erial c lock or an interrupt 2 signal. 50 lrclk miscellaneous digital audio left/ right clock. 51 mclk/int2 miscellaneous digital a dual fu n ction pin that can be configured to output an a udio m aster c lock or an interrupt 2 signal. 52 dvdd power digital core supply voltage (1.8 v). 53 scl miscellaneous digital i 2 c port serial clock input. scl is the clock line for the control port. 54 sda miscellaneous digital i 2 c port serial data input/output pin. sda is the data line for the control port. 55 int1 miscellaneous digital interrupt. this pin can be active low or active high. when status bits change, t his pin is triggered. the events that trigger an interrupt are under user configuration. 56 reset miscellaneous digital system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7611 circuitry. 57 pvdd power pll supply voltage (1.8 v) . 58 xtalp miscellaneous analog input pin for 28.63636 mhz crystal or an external 1.8 v, 28.63636 mhz clock oscillator source to clock the adv7611. 59 xtaln miscellaneous analog crystal input. input pin for 28.63 636 mhz crystal. 60 dvdd power digital core supply voltage (1.8 v). 61 cec digital input/output consumer electronic control channel. 62 ddca_scl hdmi input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. 63 ddca_sda hdmi input hdcp slave serial data port a. ddca_sda is a 3.3 v input that is 5 v tolerant. 64 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface.
adv7611 data sheet rev. d | page 10 of 16 p ower s upply s equencing power - up sequence the recommended power - up sequence of the adv7611 is to power up the 3.3 v supplies first, followed by the 1.8 v supplies. reset should be held low while the supplies are powered up. alternatively, the adv7611 may be powered up by asserting all supplies simultaneously. in this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not go above a higher rated supply level. power - down sequence the adv7611 supplies may be deasserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3.3v power supply (v) 1.8v 3.3v supplies 1.8v supplies 1.8v supplies power-up 3.3v supplies power-up 09305-007 figure 7 . recommended power - up sequence
data sheet adv7611 rev. d | page 11 of 16 functional overview hdmi receiver the receiver supports all mandatory and many optional 3d formats. it supports hdtv formats up to uxga at 8 bit . the hdmi - compatible receiver on the adv7611 incorporates programmable equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies . it is capable of equalizing fo r cable lengths up to 30 meters to achieve robust receiver performance. with the inclusion of hdcp, displays can receive encrypted video content. the hdmi interface of the adv7611 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the hdcp 1. 4 protocol. the adv7611 has a synchr onization regeneration block used to regenerate the de based on the measurement of t he video format being displaye d and to filter the horizontal and vertical synchronization signals to prevent glitches. the hdmi receiver also supports terc4 error detection, used for detection of corrupted hdmi packet s following a cable disconnect . the hdmi receiver contains an audio m ute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. on detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. audio output can be formatte d to l pcm and iec 61937 . the hdmi receiver features include: ? 162.5 mhz (uxga at 8 bit) maximum tmds clock frequency ? 3d format support defined in hdmi 1.4a specification ? integrated equalizer for cable lengths up to 30 meters ? hdcp 1. 4 ? internal hdcp keys ? pcm audio p acket support ? repeater support ? internal edid ram ? hot plug a ssert output pin for an hdmi port ? cec controller component processor the adv7611 has an any - to - any 3 3 csc matrix. the csc block is placed at the back of the cp section. csc enables yprpb - to - rgb and rgb - to - ycrcb conversions. many other standards of color space can be implemented using the color space converter. cp features include: ? 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and other formats ? manual adjustments including gain (contrast) and off set (brightness), hue , and saturation ? free run output mode that provides stable timing when no video input is present ? 162.5 mhz processing rate ? contrast, brightness, hue, and saturation controls ? standard identification enabled by stdi block ? rgb that can b e color space converted to ycrcb and decima ted to a 4:2:2 format for video - centric back end ic interfacing ? de output signal supplied for direct connection to an hdmi/dvi transmitter other features the adv7611 has hs, vs, field, and de output signals with p rogrammable position, polarity, and width . the adv7611 has programmable interrupt request output pins, including int1 and int2 (int2 is accessible only via one of following pins: mclk/int2 , sclk/int2 , or hpa_a/int2) . it also features a low power - down mod e . the i 2 c address of t he main map is 0x98 after reset. this can be changed after reset to 0x9a if pullup is attached to vs/field/alsb pin and i 2 c command sample_alsb is issued. refer to the register access and serial ports description section in the ug - 1 80. the adv7611 is provided in a 10 mm 10 mm, rohs - compliant lqfp_ep package, and is specified over the ? 40c to +85 c temperature range.
adv7611 data sheet rev. d | page 12 of 16 pixel input/output f ormatting the output section of the adv7611 is highly flexible. the pixel output bus can support up to 24 - bit 4:4:4 ycrcb. the pixel data supports both single and double data rates modes. in sdr mod e , a 16- /24 - bit 4:2:2 or 24 - bit 4:4:4 output is possible. in ddr mode 1 , the pixel output port can be configured in an 8 - /12 - bit 4:2:2 ycrcb or 24- bit 4:4:4 rgb . bus rotation is supported. table 5 and t able 6 outline the differ ent output formats that are supported. all output modes are controlled via i 2 c. 1 ddr mode is only supported only up to 50 mhz (an equivalent to data rate clocked 100 mhz clock in sdr mo de). pixel data output mo des features the output pixel por t features include : ? 8 - /12 - bit itu - r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs, a nd field output signals ? 16- /24 - bit ycrcb with embedded time codes and/or hs and vs/field pin timing ? 24- bit ycrcb/rgb with embedded time codes and/or hs and vs/field pin timing ? ddr 8 - /12 - bit 4:2:2 ycrcb ? ddr 24- bit 4:4:4 rgb table 5. sdr 4:2:2 and 4:4:4 output modes sdr 4:2:2 sdr 4:4:4 op_format_sel[7:0] 0x0 1 0x0a 1 0x80 0x8a 0x40 pixel output 8 - bit sdr itu - r bt.656 mode 0 12- bit sdr itu - r bt.656 mode 2 16- bit sdr itu - r bt.656 4:2 :2 mode 0 24- bit sdr itu - r bt.656 4:2:2 mode 2 24- bit sdr 4:4:4 mode 0 p23 high -z y3, cb3, cr3 high -z y3 r7 p22 high -z y2, cb2, cr2 high -z y2 r6 p21 high - z y1, cb1, cr1 high - z y1 r5 p20 high -z y0, cb0, cr0 high -z y0 r4 p19 high -z high -z high -z cb3, cr3 r3 p18 high -z high -z high -z cb2, cr2 r2 p17 high -z high -z high -z cb1, cr1 r1 p16 high - z high - z high - z cb0, cr0 r0 p15 y7, cb7, cr7 y11, cb11, cr11 y7 y11 g7 p14 y6, cb6, cr6 y10, cb10, cr10 y6 y10 g6 p13 y5, cb5, cr5 y9, cb9, cr9 y5 y9 g5 p12 y4 , cb4, cr4 y8, cb8, cr8 y4 y8 g4 p11 y3, cb3, cr3 y7, cb7, cr7 y3 y7 g3 p10 y2, cb2, cr2 y6, cb6, cr6 y2 y6 g2 p9 y1, cb1, cr1 y5, cb5, cr5 y1 y5 g1 p8 y0, cb0, cr0 y4, cb4, cr4 y0 y4 g0 p7 high -z high -z cb7, cr7 cb11, cr11 b7 p6 high -z high -z cb6, c r6 cb10, cr10 b6 p5 high -z high -z cb5, cr5 cb9, cr9 b5 p4 high - z high - z cb4, cr4 cb8, cr8 b4 p3 high -z high -z cb3, cr3 cb7, cr7 b3 p2 high -z high -z cb2, cr2 cb6, cr6 b2 p1 high -z high -z cb1, cr1 cb5, cr5 b1 p0 high -z high -z cb0, cr0 cb4, cr4 b0 1 modes 0x00 and 0x0a require additional writes to io map reg ister 0x19[7:6] = 2b11 and io map reg ister 0x33[6] = 1
data sheet adv7611 rev. d | page 13 of 16 t able 6. ddr 4:2:2 and 4:4:4 output modes ddr 4:2:2 mode (clock/2) ddr 4:2:2 mode (clock/2) ddr 4:4:4 mode (clock/2) 1 , 2 op_format_sel[7:0] 0x20 0x2a 0x60 8 - bit ddr itu - 656 (clock/2 output) 4:2:2 mode 0 12- bit ddr itu - 656 (cloc k/2 output) 4:2:2 mode 2 24- bit ddr rgb (clock/2 output) pixel output clock rise clock fall clock rise clock fall clock rise clock fall p23 high -z high -z cb3, cr3 y3 r7 -0 r7 -1 p22 high -z high -z cb2, cr2 y2 r6 -0 r6 -1 p21 high -z high -z cb1, cr1 y1 r5 -0 r5 -1 p20 high -z high -z cb0, cr0 y0 r4 -0 r4 -1 p19 high -z high -z high -z high -z r3 -0 r3 -1 p18 high - z high - z high - z high - z r2 - 0 r2 - 1 p17 high -z high -z high -z high -z r1 -0 r1 -1 p16 high -z high -z high -z high -z r0 -0 r0 -1 p15 cb7, cr7 y7 cb11, cr11 y11 g7 -0 g 7-1 p14 cb6, cr6 y6 cb1 0, cr10 y1 0 g6 -0 g6 -1 p13 cb5, cr5 y5 cb9, cr9 y9 g5 - 0 g5 - 1 p12 cb4, cr4 y4 cb8, cr8 y8 g4 -0 g4 -1 p11 cb3, cr3 y3 cb7, cr7 y7 g3 -0 g3 -1 p10 cb2, cr2 y2 cb6, cr6 y6 g2 -0 g2 -1 p9 cb1, cr1 y1 cb5, cr5 y5 g1 -0 g1 -1 p8 cb0, cr0 y0 cb4, cr4 y4 g0 -0 g0 -1 p7 high - z high - z high - z high - z b7 - 0 b7 - 1 p6 high -z high -z high -z high -z b6 -0 b6 -1 p5 high -z high -z high -z high -z b5 -0 b5 -1 p4 high -z high -z high -z high -z b4 -0 b4 -1 p3 high -z high -z high -z high -z b3 -0 b3 -1 p2 high -z high -z high -z high -z b2 -0 b2 -1 p1 high -z high -z high -z high -z b1 -0 b1 -1 p0 high -z high -z high -z high -z b0 -0 b0 -1 1 - 0 = even samples. 2 - 1 = odd samples.
adv7611 data sheet rev. d | page 14 of 16 outline dimensions compliant t o jedec s t andards ms-026-bcd-hd 1 16 17 32 32 49 64 48 33 12.20 12.00 sq 1 1.80 10.20 10.00 sq 9.80 1 16 17 49 64 48 33 pin 1 t op view (pins down) bot t om view (pins up) exposed p ad 06-12-2012- a view a 1.60 max sea ting plane 0.75 0.60 0.45 1.00 ref 0.15 0.05 0.08 coplanarity 7 0 0.20 0.09 view a rotated 90 ccw 1.45 1.40 1.35 0.27 0.22 0.17 0.50 lead pitch 7.50 ref sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 5.10 5.00 sq 4.90 figure 8 . 64 - lead low profile quad flat package (lqfp_ep) sw - 64 - 2 dimensions shown in millimeters orde ring guide model 1 , 2 notes temperature range package description package option adv7611bswz ? 40c to +85c 64- lead lqfp_ep sw -64-2 adv7611bswz - rl 3 ? 40c to +85c 64- lead lqfp_ep sw -64-2 adv7611bswz - p 4 ? 40c to +85c 64- lead lqfp_ep sw -64-2 adv7611bs wz - p -rl 3 ? 40c to +85c 64- lead lqfp_ep sw -64-2 adv7611wbswz ? 40c to +85c 64- lead lqfp_ep sw -64-2 adv7611wbswz -rl 3 ? 40c to +85c 64- lead lqfp_ep sw -64-2 eval - adv7611eb1z evaluatio n board with hdcp keys eval - adv7611eb2z evaluation board without hdcp keys 1 z = rohs compliant part. 2 w = qualified for automotive parts. 3 13 tape and reel. 4 non - hdcp version. automotive products the ad v 7611w model s are available with controlled manufacturing to support the qual ity and reliability requirement s of automotive applications. note that th e s e automotive model s may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade product s shown are avai lable for use in automotive applications. contact your local analog devices, inc., account representative for specific product ordering inform ation and to obtain the specific automotive reliability report for this model.
data sheet adv7611 rev. d | page 15 of 16 notes
adv7611 data sheet rev. d | page 16 of 16 notes hdmi, the hdmi l ogo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ? 2010 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09305 - 0 - 6/12(d)

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